The 3PAR ASIC now and the future

A great article appeared in The Register recently previewing the HPE 3PAR GEN 6 ASIC. It sparked my interest as it not only gave some clues to the direction of 3PAR but reminded me that I hadn’t written a post yet covering the ASIC. So this is a post of two halves, the first covering the background and architectural importance of the ASIC followed by a summary of the GEN 6 news and what clues it may give us to the future.

3PAR ASIC Overview

I have heard HPE staff describe 3PAR’s ASIC as its secret sauce many times, what is for certain is that it’s right at the heat of its architecture. Let’s start at the beginning, an ASIC stands for Application Specific Integrated Circuit, this describes quite succinctly what it is – an integrated circuit which has been customised for a specific use.

 

As an ASIC is hardware based having this at the heart of your architecture is not a decision to be taken likely, since you need to design it not only to deliver the features you require today but for the life cycle of that model i.e. 5+ years. Software based vendors have long argued that their approach is simpler and does not require the skill of predicting the future, if you need a new feature write it in. When I have been lucky enough to meet the 3PAR development team they have said on a number of occasions that they always consider the future of the ASIC in each new generation, but that so far they still believe that the ASIC is the best design for now and moving into the future.

ASIC

 

The models over the past few years feature the ASIC generation as follows:

  • 3PAR 8000 and 20, 000 – GEN 5
  • 3PAR 7000 and 10,000 – GEN 4
  • 3PAR F and T – GEN3
  • Generations before – I am too young to remember

 

To give you a feel for some of the features that currently harness the ASIC and the benefit they deliver I have summarised below:

  • Persistent checksum – don’t let my data corrupt
  • Mixed I/O processing – let me do BIG and little transactions without losing performance
  • Zero detect – one weird trick to stay thin
  • Dedupe – no doppelgangers, one of anything is enough
  • RAID parity calculations – stripe me like it’s hot

Key Gen 6 news

  • GEN6 Expected to Ship in 2018, it would seem logical this will be when the next generation of 3PAR will also ship
  •  The ASIC will be designed to be media agnostic and cope with all comers. This again continues down the current line of thinking of making 3PAR an I/O processing machine and will be important with 3D XPoint and memoristors round the corner
  • Improvements in storage networking such as NVMe will drive the need for even faster storage devices
  • Data services such as SnapShots will aim to complete quicker again to meet this future need for speed

Do take the time to check out the excellent full article on The Register.

Published by

3 thoughts on “The 3PAR ASIC now and the future

Leave a Reply

Your email address will not be published. Required fields are marked *